This invention relates to the high speed performance of numerical calculations, and in particular to hardware and methods of efficiently implementing numerical operations in digital processing devices.
In the design of digital processing apparatus, operations calling for arithmetical operations on numbers pose special problems. Even an elementary binary operation such as multiplication can require a great number of steps for its implementation. For this reason, multiplication, for example, is usually carried out by special hardware units, such as a floating point processing chip that receives two n-bit input numbers, and provides a number of output words that in turn are combined to yield the n most significant bits of the product of the two numbers. Such chips generally split the arithmetical operation into a number of simpler operations on components of the input numbers, and combine the results of these simpler operations, thus operating in parallel to arrive at an output in fewer levels of computation, or in less time.
In the case of a floating point n-bit multiplier, the product of two n-bit numbers containing 2n bits, is output as an n-bit number, entailing the sacrifice of information contained in the lesser bits. In order to control the propagation of errors when many arithmetical operations are performed in succession, the lesser bits must be inspected and some form of rounding-off operation performed.
To maintain consistency among floating-point coprocessors, the IEEE/ANSI has promulgated Standard 754 for binary floating-point arithmetic operations and rounding-off of computed values. The default rounding mode of this Standard requires that the n-bit representation nearest to the infinitely precise result shall be delivered; if the two nearest values are equally near, then the one with its least significant bit equal to zero shall be delivered. This is a "nearest/even" rounding off rule. Several other optional rounding modes are also specified in the Standard.
In practice, this Standard is implemented by inspecting the least significant bits of a calculation and determining whether a given rounding mode requires truncating, shifting, addition of one bit, or the like. The least significant bits are inspected and a control signal based on their content is generated to control the rounding off operation, so that the rounding off algorithms need only be invoked for words meeting a threshold value of significance.
One common control signal, the so-called sticky bit, is defined by
0 if all bits to the right of the sticky=least significant bit are zero, and PA1 1 otherwise
where "least significant bit" is here used to mean the least of the n most significant bits, or the rounding off bit position.
Computationally this sticky bit is determined by a carry propagate addition on all the less significant bits of the units LSB output words to obtain their sum, followed by a logical OR of all bits to the right of the rounding-off position in the LSB sum. However, the degree of processing required to form the necessary addition entails rather large-area circuit elements and a large number of sequential steps. For example an n-bit adder requires at least log.sub.2 (n) successive steps for its processing.
Accordingly it is desirable to determine control signals of this sort in a more efficient fashion.